mental improvements during the same period. What is clearly needed in verification techniques and technology is the equivalent of a synthesis productivity breakthrough. In the second edition of Writing Testbenches, Bergeron raises the verification level of abstraction by introducing coverage-driven constrained-random transaction-level self-checking testbenches- all made possible through the introduction of hardware verification languages (HVLs), such as e from Verisity and Open Vera from Synopsys. The state-of-art methodologies described in Writing Test- benches will contribute greatly to the much-needed equivalent of a synthesis breakthrough in verification productivity. I not only highly recommend this book, but also I think it should be required reading by anyone involved in design and verification of today’s ASIC, So Cs and systems. Harry Foster Chief Architect Verplex Systems, Inc. xviii Writing Testbenches: Functional Verification of HDL Models PREFACE If you survey hardware design groups, you will learn that between 60% and 80% of their effort is now dedicated to verification.
€252.92
यह ईबुक खरीदें और 1 और मुफ़्त पाएं!
भाषा अंग्रेज़ी ● स्वरूप PDF ● ISBN 9781461503026 ● प्रकाशक Springer US ● प्रकाशित 2012 ● डाउनलोड करने योग्य 3 बार ● मुद्रा EUR ● आईडी 4671315 ● कॉपी सुरक्षा Adobe DRM
एक DRM सक्षम ईबुक रीडर की आवश्यकता है
एक ही लेखक से अधिक ईबुक / संपादक
9,464 इस श्रेणी में ईबुक
