As Moore’s law continues to unfold, two important trends have recently emerged. First, the growth of chip capacity is translated into a corresponding increase of number of cores. Second, the parallelization of the computation and 3D integration technologies lead to distributed memory architectures. This book describes recent research that addresses urgent challenges in many-core architectures and application mapping. It addresses the architectural design of many core chips, memory and data management, power management, design and programming methodologies. It also describes how new techniques have been applied in various industrial case studies.
Table of Content
Part I: HS/SW/ Building Blocks: Architecture, Methods, and Techniques.- 1. Memory Architecture and Management in an No C Platform.- 2. Application-Specific Multi-Threaded Dynamic Memory Management.- 3. Power Management Architecture in Mc No C.- 4. ASIP Exploration and Design.- Part II: System-level Exploration.- 5. System Exploration.- 6. MPA: Parallelization Made Easy.- Part III: Industrial Applications.- 7. MPSo C Architecture Performance Analysis for Agile SDR Radio Applications.- 8. Application of the MOSART Flow on the Wi MAX (802.16e) PHY.
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