Autor: John Jose

Maurizio Palesi is currently Associate Professor in Computer Engineering, Department of Electrical, Electronics and Computer Engineering, Università degli Studi di Catania, Catania, Italy. Prior to this he worked as Associate Professor in Computer Engineering, Università degli Studi di Enna, KORE, Italy. He completed his Ph D Degree in Computer Engineering, Università degli Studi di Catania, Italy and Diploma di Laurea (five years degree) in Computer Engineering, (grade 110/110 e lode), Università degli Studi di Catania, Italy.  He has supervised more than 50 students for the Master Degree in Computer Engineering.  He is external co-supervisor for Ph.D. in Electrical Engineering of students from School of Graduate Studies, Universiti Teknologi Malaysia. He is part of foreign evaluator panel of the Ph D program in Computer Engineering and Electrical Engineering at the Department of Electrical Engineering, COMSATS Institute of Information Technology (CIIT), Islamabad, Pakistan. He has also been member of the commission for the international Ph D exam of students. In 2011 he received the Best Paper Award for his paper “Run-time Deadlock Detection in Networks-on-Chip using Coupled Transitive Closure Networks” presented at the Design Automation and Test in Europe (DATE 2011) on 14-18 March 2011, at Grenoble, France. In 2014  he received Hi PEAC Paper Award for his paper “System-Level Hierarchy in Run-Time Fault-Aware Management of Many-Core Systems” presented at Design Automation Conference (DAC). He also received the Outstanding Reviewer award to be within the top 10th percentile of reviewers for the Elsevier Computers & Electrical Engineering Journal, in terms of the number of manuscript reviews completed in the last two years in 2014. He is presently Member of the European Network on High Performance and Embedded Architecture and Compilation (Hi PEAC) and also IEEE Senior Member which is an honor bestowed only to those who have made significant contributionsto the profession. He is also a co-editor in various reputed International journals. He has also published numerous papers in national and international journals.   Ljiljana Trajkovic received the Dipl. Ing. degree from University of Pristina, Yugoslavia, in 1974, the M.Sc. degrees in electrical engineering and computer engineering from Syracuse University, Syracuse, NY, in 1979 and 1981, respectively, and the Ph.D. degree in electrical engineering from University of California at Los Angeles, in 1986. She is currently a Professor in the School of Engineering Science at Simon Fraser University, Burnaby, British Columbia, Canada. From 1995 to 1997, she was a National Science Foundation (NSF) Visiting Professor in the Electrical Engineering and Computer Sciences Department, University of California, Berkeley. She was a Research Scientist at Bell Communications Research, Morristown, NJ, from 1990 to 1997, and a Member of the Technical Staff at AT&T Bell Laboratories, Murray Hill, NJ, from 1988 to 1990. Her research interests include high-performance communication networks, control of communication systems, computer-aided circuit analysis and design, and theory of nonlinear circuits and dynamical systems. Dr. Trajkovic serves as IEEE Division X Delegate/Director (2019–2020) and served as IEEE Division X Delegate-Elect/Director-Elect (2018). She served as Senior Past President (2018–2019), Junior Past President (2016–2017), President (2014–2015), President-Elect (2013), Vice President Publications (2012–2013, 2010–2011), Vice President Long-Range Planning and Finance (2008–2009), and a Member at Large of the Board of Governors (2004–2006)of the IEEE Systems, Man, and Cybernetics Society. She served as 2007 President of the IEEE Circuits and Systems Society and a member of its Board of Governors (2004–2005, 2001–2003). She is Chair of the IEEE Circuits and Systems Society joint Chapter of the Vancouver/Victoria Sections. She was Chair of the IEEE Technical Committee on Nonlinear Circuits and Systems (1998).She is General Co-Chair of SMC 2020 and SMC 2020 Workshop on BMI Systemsand served as General Co-Chair of SMC 2019 and SMC 2018 Workshops on BMI Systems, SMC 2016, and HPSR 2014, Special Sessions Co-Chair of SMC 2017, Technical Program Chair of SMC 2017 and SMC 2016 Workshops on BMI Systems, Technical Program Co-Chair of ISCAS 2005, and Technical Program Chair and Vice General Co-Chair of ISCAS 2004. She served as an Associate Editor of the IEEE Transactions on Circuits and Systems (Part I) (2004–2005, 1993–1995), the IEEE Transactions on Circuits and Systems (Part II) (2018, 2002-2003, 1999–2001), and the IEEE Circuits and Systems Magazine (2001–2003). She was a Distinguished Lecturer of the IEEE Circuits and Systems Society (2010–2011, 2002–2003). She is a Professional Member of IEEE-HKN and a Life Fellow of the IEEE.   Dr.Jayakumari.J is presently working as Professor, Department of Electronics and Communication Engineering, Mar Baselios College of Engineering and Technology, Nalanchira, Thiruvananthapuram, Kerala. She obtained her B.E (ECE) from M.S. University, Tirunelveli in 1994, M.Tech (Applied Electronics and Instrumentation) in 1998 and Ph D (ECE) in 2009 from Kerala University. She have teaching experience of more than 23 years and  research experience of 15 years . Her major areas of research interests include Wireless communication, coding techniques, signal and Image processing. She has published more than 75 papers in International Journals and Conferences. She is a senior member of IEEE, Fellow of IETE, IE (I) and CET (I), Chartered Engineer of IE (I) and Member, The Society of Digital Information and Wireless Communications (SDIWC). She is also an Academic Council member of the Council of Engineering and Technology(India).   Dr. John Jose is an Assistant Professor in Department of Computer Science & Engineering, Indian Institute of Technology, Guwahati, Assam since 2015. Prior to this he worked as an Assistant Professor in Rajagiri School of Engineering and Technology, Kochi for 2 years and Viswajyotjhi College of Engineering and Technology, Muvattupuzha, Kerala for 5 years. After completing his schooling from Vimalalayam and De Paul schools from Thodupuzha, Kerala he did his pre degree course from Mar Ivanios College Trivandrum. He did his B.Tech degree in CSE from College of Engineering Adoor, Cochin University, Kerala. He was a rank holder in M.Tech degree from Vellore Institute of Technology (VIT University). He completed his Ph.D degree in Department of Computer Science & Engineering, Indian Institute of Technology Madras. He had guided over 8 M.Tech thesis and is currently supervising 6 Ph.D thesis and 2 M.Tech thesis. His area of interests is in on-chip interconnection networks and cache management techniques for large multicore systems. He is the principal investigator of two sponsored R&D projects funded by DST, Govt of India. He is having active research collaboration with University of Catania, Italy, University of Essex, UK, Colorado State University, USA, and Cochin University. During his doctoral studies in CSE department, IIT Madras he has received the outstanding teaching assistant award for eight consecutive semesters. He is a reviewer for many national and international peer reviewed journals and member of technical program committee for many IEEE/ACM national and international conferences. He is a resource person to computer architecture related symposia and workshops in many technical institutes all over India. He has given many technical presentations in various international conferences held at Brazil, UAE, Singapore, France, Italy, South Korea and United States in the fields of computer design, interconnection networks, and design automation. He has co-authored 25 international IEEE & ACM conference publications and 5 per reviewed journal papers to his credit. He is the recipientof ACM-SIGDA, IEEE-CEDA, Indian Association for Research in Computer Science (IARCS) and DRDO grants for various research presentations held in various international venues. He is the IIT Guwahati coordinator for Ishan Vikas program of MHRD, Govt. of India and course coordinator for MHRD sponsored GIAN course in Scalable on chip Interconnects. He has offered the NPTEL course in Multicore Computer Architecture: storage and interconnects.  He is a resource person for many career guidance seminars/ workshops to various technical institutes and schools. He is a motivational speaker for many companies, school and higher education institutions. He is an active member of professional societies like ACM, IEEE, ISTE and CSI.