Functional verification has become an important aspect of the chip design process. Significant resources, both in industry and academia, are devoted to the design complexity and verification endeavors.
SAT-Based Scalable Formal Verification Solutions discusses in detail several of the latest and interesting scalable SAT-based techniques including: Hybrid SAT Solver, Customized Bounded/Unbounded Model Checking, Distributed Model Checking, Proofs and Proof-based Abstraction M...
Tabla de materias
Design Verification Challenges.- Design Verification Challenges.- Background.- Basic Infrastructure.- Efficient Boolean Representation.- Hybrid DPLL-Style SAT Solv...
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Idioma Inglés ● Formato PDF ● Páginas 330 ● ISBN 9780387691671 ● Tamaño de archivo 5.8 MB ● Editorial Springer US ● Ciudad NY ● País US ● Publicado 2007 ● Descargable 24 meses ● Divisa EUR ● ID 2145487 ● Protección de copia DRM social