Addresses the Challenges Associated with System-on-Chip Integration Network-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (No C), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (So C...
Addresses the Challenges Associated with System-on-Chip Integration Network-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (No C), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (So C). This book provides a basic overview of topics associated with No C-based design: communication infrastructure design, communication methodology, evaluation framework, and mapping of applications onto No C. It details the design and evaluation of different proposed No C structures, low-power techniques, signal integrity and reliability issues, application mapping, testing, and future trends.Utilizing examples of chips that have been implemented in industry and academia, this text presents the full architectural design of components verified through implementation in industrial CAD tools. It describes No C research and developments, incorporates theoretical proofs strengthening the analysis procedures, and includes algorithms used in No C design and synthesis. In addition, it considers other upcoming No C issues, such as low-power No C design, signal integrity issues, No C testing, reconfiguration, synthesis, and 3-D No C design. This text comprises 12 chapters and covers: The evolution of No C from So C-its research and developmental challenges No C protocols, elaborating flow control, available network topologies, routing mechanisms, fault tolerance, quality-of-service support, and the design of network interfaces The router design strategies followed in No Cs The evaluation mechanism of No C architectures The application mapping strategies followed in No Cs Low-power design techniques specifically followed in No Cs The signal integrity and reliability issues of No C The details of No C testing strategies reported so far The problem of synthesizing application-specific No Cs Reconfigurable No C design issues Direction of future research and development in the field of No C Network-on-Chip: The Next Generation of System-on-Chip Integration covers the basic topics, technology, and future trends relevant to No C-based design, and can be used by engineers, students, and researchers and other industry professionals interested in computer architecture, embedded systems, and parallel/distributed systems.
