This book describes analytical models and estimation methods to enhance performance estimation of pipelined multiprocessor systems-on-chip (MPSo Cs). A framework is introduced for both design-time and run-time optimizations. For design space exploration, several algorithms are presented to minimize the area footprint of a pipelined MPSo C under a latency or a throughput constraint. A novel adaptive pipelined MPSo C architecture is described, where idle processors are transitioned into low-power states at run-time to reduce energy consumption. Multi-mode pipelined MPSo Cs are introduced, where multiple pipelined MPSo Cs optimized separately are merged into a single pipelined MPSo C, enabling further reduction of the area footprint by sharing the processors and communication buffers. Readers will benefit from the authors’ combined use of analytical models, estimation methods and exploration algorithms and will be enabled to explore billions of design points in a few minutes.
Table of Content
Introduction.- Literature Survey.- Optimisation Framework.- Performance Estimation of Pipelined MPSo Cs.- Design Space Exploration of Pipelined MPSo Cs.- Adaptive Pipelined MPSo Cs.- Power Management in Adaptive Pipelined MPSocs.- Multi-mode Pipelined MPSo Cs.- Conclusions and Future Work.
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