Why learn and use Verilog if you’re a student, beginning designer, or leading edge systems designer? The naive would ignore Verilog and "standardize" by using VHDL, the result of a decade-long committee design process. A single language for the whole world would appear to: ease the training of designers and others who use descriptions, increase tool competition to lower costs, and increase design sharing and library usage. Further, the U. S. Department of Defense (DOD) mandated its use for design description Mandated standards rarely are best, and often not very good. Competition is good because it encourages rapid evolution. Also, we know that evolved, de facto standards embodied in a time-tested product based on initial conceptual clarity from one person or organization versus de jure standards coming from large committees or government mandates are often preferred. A standard must be "open" so that many others can use it, build on it, and compete to make it better. One only has to compare: C, C++, and FORTRAN versus ADA (DOD’s mandated language), PLl; TCP/IP versus OSI; the Intel X86 or Power PC microprocessors versus DOD’s many architectures; Windows versus the many UNIX dialects; and various industry buses versus DOD’s Futurebus. Verilog, introduced in 1985, was developed by one person, Phil Moorby at Gate- way Design Automation. It was Phil’s third commercial logic simulator.
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