Verification Methodology Manual for SystemVerilog

Janick Bergeron & Eduard Cerny

Janick Bergeron & Eduard Cerny
Verification Methodology Manual for SystemVerilog [PDF ebook]

Apoio

Capa do Janick Bergeron & Eduard Cerny: Verification Methodology Manual for SystemVerilog (PDF)

Functional verification remains one of the single biggest challenges in the development of complex system-on-chip (So C) devices. Despite the introduction of successive new technologies, the gap between design capability and verification confidence continues to widen. The biggest problem is that these diverse new technologies have led to a proliferation of verification point tools, most with their own languages and methodologies.

Fortunately, a solution is at hand. System Ver...

Functional verification remains one of the single biggest challenges in the development of complex system-on-chip (So C) devices. Despite the introduction of successive new technologies, the gap between design capability and verification confidence continues to widen. The biggest problem is that these diverse new technologies have led to a proliferation of verification point tools, most with their own languages and methodologies.

Fortunately, a solution is at hand. System Verilog is a unified language that serves both design and verification engineers by including RTL design constructs, assertions and a rich set of verification constructs. System Verilog is an industry standard that is well supported by a wide range of verification tools and platforms. A single language fosters the development of a unified simulation-based verification tool or platform.

Consolidation of point tools into a unified platform and convergence to a unified language enable the development of a unified verification methodology that can be used on a wide range of So C projects. ARM and Synopsys have worked together to define just such a methodology in the Verification Methodology Manual for System Verilog. This book is based upon best verification practices by ARM, Synopsys and their customers.

Verification Methodology Manual for System Verilog is a blueprint for verification success, guiding So C teams in building a reusable verification environment taking full advantage of design-for-verification techniques, constrained-random stimulus generation, coverage-driven verification, formal verification and other advanced technologies to help solve their current and future verification problems.

This book is appropriate for anyone involved in the design or verification of a complex chip or anyone who would like to know more about the capabilities of System Verilog. Following the Verification Methodology Manual for System Verilog will give So C development teams and project managers the confidence needed to tape out a complex design, secure in the knowledge that the chip will function correctly in the real world.

Tabela de Conteúdo

Verification Planning.- Assertions.- Testbench Infrastructure.- Stimulus and Response.- Coverage-Driven Verification.- Assertions for Formal Tools.- System-Level ...

Sobre o autor

Janick Bergeron is a Scientist at Synopsys, Inc. He is the author of the best-selling book Writing Testbenches: Functional Verification of HDL Models and the moderator...

Sobre o autor

Janick Bergeron is a Scientist at Synopsys, Inc. He is the author of the best-selling book Writing Testbenches: Functional Verification of HDL Models and the moderator of the Verification Guild. Prior to joining Synopsys, Janick worked on verification methodology at Qualis Design Corporation and Bell-Northern Research. He holds a Masters degree in Electrical Engineering from the University of Waterloo, a Bachelor of Science degree in Engineering from the Université du Québec, and an MBA degree granted through the University of Oregon.
Eduard Cerny is a Principal Engineer, R&D, in the Verification Group at Synopsys, Inc. He joined Synopsys in 2001 after 25 years in academia, as Professor of Computer Science at the Université de Montréal. Eduard has a B.Sc. in Electrical Engineering from Loyola College in Montreal, Canada, and a M.Eng. and Ph.D. in Electrical Engineering from Mc Gill University in Montreal, Canada. His interests have been in design, verification and test of hardware, and he is author of many articles in these areas.
Alan Hunter, BEng(Hons), MSc, is the Design Verification Methodology Programme manager at ARM Ltd. and is leading the design verification methodology work for ARM worldwide. This work covers all areas from CPU design verification through systems and system component design verification. His main areas of interest include optimizing design verification efficiency and quality, formal methods, and determinism in the design verification flow. Prior to joining ARM, Alan worked for a small formal verification company specializing in property and equivalence checking.
Andy Nightingale, BEng(Hons), MBCS CITP, is a consultant engineer at ARM Ltd and has led the So C Verification group in ARM’s Cambridge and Sheffield design centers for the past four years. The group covers ARM Prime XSys platforms and Prime Cell development, including advanced AXI- and AHB-based system backplanecomponents such as bus interconnects and high-performance memory controllers. Prior to working at ARM, Andy worked as a real-time embedded systems engineer for a successful scientific instrument company, primarily serving the semiconductor industry.