This book addresses the need for energy-efficient amplifiers, providing gain enhancement strategies, suitable to run in parallel with lower supply voltages, by introducing a new family of single-stage cascode-free amplifiers, with proper design, optimization, fabrication and experimental evaluation. The authors describe several topologies, using the UMC 130 nm CMOS technology node with standard-VT devices, for proof-of-concept, achieving results far beyond what is achievable with a classic single-stage folded-cascode amplifier. Readers will learn about a new family of circuits with a broad range of applications, together with the familiarization with a state-of-the-art electronic design automation methodology used to explore the design space of the proposed circuit family.
Table of Content
Introduction.- Background and State-of-the-art.- Proposed Architectures and Practical Realizations.- Optimization Design and Simulation Results.- Integrated Prototypes and Experimental Evaluation.- Conclusions.
About the author
Ricardo F. S. Póvoa is a Post-Doctoral Researcher in the Integrated Circuits Group, within the Instituto de Telecomunicações, Lisboa, Portugal.João C. da Palma Goes is a Professor at Faculdade de Ciências e Tecnologia, Universidade Nova de Lisboa, Lisboa, Portugal.Nuno C. G. Horta is a Professor at Instituto Superior Técnico, Universidade de Lisboa, and a Senior Researcher in the Integrated Circuits Group, within the Instituto de Telecomunicações, Lisboa, Portugal.
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