Chapter 1. Arithmetic Satisfiability-Modulo-Theory Solving Applied to Non-Standard Analysis Problems of Cyber-Physical Systems.- Chapter 2. Fast AIG-based Approximate Logic Synthesis.- Chapter 3. External Don’t Cares in Logic Synthesis.- Chapter 4. Maiorana-Mc Farland Boolean Bent Functions Characterized by their Reed-Muller Spectra.- Chapter 5. Towards System-level Assertions for Heterogeneous Systems.- Chapter 6. SAT-based Key Determination Attack for Improving the Quality Assessment of Logic Locking Mechanisms.- Chapter 7.  Autosymmetric and D-reducible Functions: Theory and Application to Security.- Chapter 8. Two-operands modular multiplication to small bit-ranges.- Chapter 9. Low Latency Real-Time Inference for Multilayer Perceptrons on FPGAs.- Chapter 10. Thirty-six Officers of Euler — New Insights Computed Using XBOOLE.- Chapter 11. Start Small but Dream Big: On Choosing a Static Variable Order for Multiplier BDDs.

Rolf Drechsler received the Diploma and Dr. phil. nat. degrees in computer science from the Johann Wolfgang Goethe University in Frankfurt am Main, Germany, in 1992 and 1995, respectively. He worked at the Institute of Computer Science, Albert-Ludwigs University, Freiburg im Breisgau, Germany, from 1995 to 2000, and at the Corporate Technology Department, Siemens AG, Munich, Germany, from 2000 to 2001.  Since October 2001, Rolf Drechsler is Full Professor and Head of the Group of Computer Architecture, Institute of Computer Science, at the University of Bremen, Germany. In 2011, he additionally became the  Director of the Cyber-Physical Systems Group at the German Research Center for Artificial Intelligence (DFKI) in Bremen.  His current research interests include the development and design of data structures and algorithms with a focus on circuit and system design. He is an IEEE Fellow.
  Sebastian Huhn received the B.S. and M.S. degrees and the Dr.-Ing. doctorate degrees in computer engineering from the University of Bremen, Bremen, Germany, in 2012, 2014, and 2020, respectively. He is currently a Post Doc in the Group of Computer Architecture at this university and a Senior Researcher at the German Research Center for Artificial Intelligence (DFKI), Bremen. His current research interests include design for test, reliability, and debug, in particular, novel test generation, test interfaces and pattern retargeting techniques. Besides this, he is interested in formal techniques, formal reliability analysis & enhancement of complex systems and circuits.