3 หนังสืออิเล็กทรอนิกส์โดย S. Sapatnekar
Sung-Mo (Steve) Kang & S. Sapatnekar: Design Automation for Timing-Driven Layout Synthesis
Moore’s law [Noy77], which predicted that the number of devices in- tegrated on a chip would be doubled every two years, was accurate for a number of years. Only recently has the level of integration …
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€165.79
Naresh Maheshwari & S. Sapatnekar: Timing Analysis and Optimization of Sequential Circuits
Recent years have seen rapid strides in the level of sophistication of VLSI circuits. On the performance front, there is a vital need for techniques to design fast, low-power chips with minimum area …
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€114.60
Ding-Zhu Du & Bing Lu: Layout Optimization in VLSI Design
Introduction The exponential scaling of feature sizes in semiconductor technologies has side-effects on layout optimization, related to effects such as inter- connect delay, noise and crosstalk, sign …
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€166.45