Vijay Nath & J. K. Mandal 
Nanoelectronics, Circuits and Communication Systems [PDF ebook] 
Proceeding of NCCS 2018

Broad band Capacitive Coupling Antenna For C-Band Applications.- A Novel Super-Resolution Reconstruction from Multiple Frames via Sparse Representation.- Multi-class Cancer Classification in Microarray Datasets using MI-based feature selection and Artificial Neural Network.- Design and Implementation of an Accurate 3- bit System on Chip (So C) Flash ADC for Aerospace Application in 90nm CMOS Technology .- Automatic Bird Species Recognition based on Spiking Neural Network.- A Current Mode VCO Design Approach for Higher Oscillation Frequency.- Study & Design of Smart City with Internet of Things: A Review.

Dr. Vijay Nath received his bachelor’s degree in Physics and master’s degree in Electronics from DDU Gorakhpur University, India, in 1998 and 2001. He also completed his PGDCN (GM) at MMMUT Gorakhpur in 1999. He received his Ph.D. degree in VLSI Design & Technology from Dr. RML Avadh University Ayodhya in association with CEERI Pilani in 2008. From 2000 to 2001, he was a project trainee at the IC Design Group CEERI Pilani under the guidance of Dr. K.S. Yadav (Senior Scientist). From 2002 to 2006, he severed as faculty at the Department of Electronics, DDU University Gorakhpur. In 2006, he joined the Department of ECE, BIT Mesra, Ranchi (JH), India. Presently, he is the Professor In-charge of the Embedded System Design Lab, an Adviser of NAPS (News & Publication Society), member of BIT Mesra Brand Management, Faculty Adviser to the IEI Student Chapter (ECE) BIT Mesra, and Honorary Secretary of the IETE Ranchi Centre. He has been honored with the Vivekananda Techno Fiesta Award-2002, Young Scientist Award-2004, CCSN Best Paper Award-2013, First Prize in the IEI Technical Contest-2013, and Cadence Design Contest-2014 and 2016.

His research interests include microelectronics, nanoelectronics, analog, digital and mixed CMOS VLSI circuits, low-power VLSI circuits, ultra-low-power CMOS temperature sensors, ASICs, embedded systems designs, smart cardiac pacemakers, smart grids, the Internet of Things, and machine learning. He has to his credit over 150 publications in reputed Scopus & SCI journals and Scopus books and conference proceedings. He has successfully completed two R&D projects funded by the DST New Delhi jointly with the DRDL Hyderabad and MHRD New Delhi, and a third project is currently underway, funded by RESPOND SAC ISRO Ahmadabad, Government of India. He has edited 5 books published by Springer. He is a member of several professional societies and academic bodies including IETE, ISTE, ISVE, and IEEE.

Prof. J.K. Mandal received his M.Sc. in Physics from Jadavpur University in 1986 and his M.Tech. in Computer Science from the University of Calcutta, and was subsequently awarded a Ph.D. in Computer Science and Engineering by Jadavpur University in 2000. Currently, he is a Professor of Computer Science and Engineering and was Dean of the Faculty of Engineering, Technology and Management, Kalyani University, West Bengal, for two consecutive terms. He started his career as a Lecturer at NERIST, Arunachal Pradesh, in 1988, and has 30 years of teaching and research experience. His focus areas include coding theory, data and network security, remote sensing and GIS-based applications, data compression, error correction, visual cryptography, steganography, security in MANET, wireless networks, and unified computing. He is a life member of the Computer Society of India and a fellow of the IETE. He has edited more than 30 proceedings volumes, 360 articles, and 6 books. He is one of the editors forthe Springer AISC and CCIS Series.