Janick Bergeron is a Scientist at Synopsys, Inc. He is the author of the best-selling book Writing Testbenches: Functional Verification of HDL Models and the moderator of the Verification Guild. Prior to joining Synopsys, Janick worked on verification methodology at Qualis Design Corporation and Bell-Northern Research. He holds a Masters degree in Electrical Engineering from the University of Waterloo, a Bachelor of Science degree in Engineering from the Université du Québec, and an MBA degree granted through the University of Oregon.
Eduard Cerny is a Principal Engineer, R&D, in the Verification Group at Synopsys, Inc. He joined Synopsys in 2001 after 25 years in academia, as Professor of Computer Science at the Université de Montréal. Eduard has a B.Sc. in Electrical Engineering from Loyola College in Montreal, Canada, and a M.Eng. and Ph.D. in Electrical Engineering from Mc Gill University in Montreal, Canada. His interests have been in design, verification and test of hardware, and he is author of many articles in these areas.
Alan Hunter, BEng(Hons), MSc, is the Design Verification Methodology Programme manager at ARM Ltd. and is leading the design verification methodology work for ARM worldwide. This work covers all areas from CPU design verification through systems and system component design verification. His main areas of interest include optimizing design verification efficiency and quality, formal methods, and determinism in the design verification flow. Prior to joining ARM, Alan worked for a small formal verification company specializing in property and equivalence checking.
Andy Nightingale, BEng(Hons), MBCS CITP, is a consultant engineer at ARM Ltd and has led the So C Verification group in ARM’s Cambridge and Sheffield design centers for the past four years. The group covers ARM Prime XSys platforms and Prime Cell development, including advanced AXI- and AHB-based system backplanecomponents such as bus interconnects and high-performance memory controllers. Prior to working at ARM, Andy worked as a real-time embedded systems engineer for a successful scientific instrument company, primarily serving the semiconductor industry.
4 Електронні книги від Janick Bergeron
Janick Bergeron & Eduard Cerny: Verification Methodology Manual for SystemVerilog
Functional verification remains one of the single biggest challenges in the development of complex system-on-chip (So C) devices. Despite the introduction of successive new technologies, the gap betw …
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€106.99
Janick Bergeron: Writing Testbenches using SystemVerilog
If you survey hardware design groups, you will learn that between 60% and 80% of their effort is dedicated to verification. This may seem unusually large, but I include in ‘verification’ all debuggin …
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Англійська
€128.39
Janick Bergeron: Writing Testbenches: Functional Verification of HDL Models
mental improvements during the same period. What is clearly needed in verification techniques and technology is the equivalent of a synthesis productivity breakthrough. In the second edition of Writi …
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€257.15
Janick Bergeron: Writing Testbenches
CHAPTER 6 Architecting Testbenches 221 Reusable Verification Components 221 Procedural Interface 225 Development Process 226 Verilog Implementation 227 Packaging Bus-Functional Models 228 Utility Pac …
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DRM
€114.58