Jun Kyong Kim & Kangmin Lee 
Low-Power NoC for High-Performance SoC Design [PDF ebook] 

Chip Design and Implementation from a Practical Viewpoint Focusing on chip implementation, Low-Power No C for High-Performance So C Design provides practical knowledge and real examples of how to use network on chip (No C) in the design of system on chip (So C). It discusses many architectural and theoretical studies on No Cs, including design methodology, topology exploration, quality-of-service guarantee, low-power design, and implementation trials. The Steps to Implement No C The book covers the full spectrum of the subject, from theory to actual chip design using No C. Employing the Unified Modeling Language (UML) throughout, it presents complicated concepts, such as models of computation and communication-computation partitioning, in a manner accessible to laypeople. The authors provide guidelines on how to simplify complex networking theory to design a working chip. In addition, they explore the novel No C techniques and implementations of the Basic On-Chip Network (BONE) project. Examples of real-time decisions, circuit-level design, systems, and chips give the material a real-world context. Low-Power No C and Its Application to So C Design Emphasizing the application of No C to So C design, this book shows how to build the complicated interconnections on So C while keeping a low power consumption.