Model based testing is the most powerful technique for testing hardware and software systems. Models in Hardware Testing describes the use of models at all the levels of hardware testing. The relevant fault models for nanoscaled CMOS technology are introduced, and their implications on fault simulation, automatic test pattern generation, fault diagnosis, memory testing and power aware testing are discussed. Models and the corresponding algorithms are considered with respect to the most recent state of the art, and they are put into a historical context by a concluding chapter on the use of physical fault models in fault tolerance.
Mục lục
Contributing Authors. Preface. To Christian: a Real Test & Taste Expert. From LAAS to LIRMM and Beyond. 1: Open Defects in Nanometer Technologies; J. Figueras, et al. 2: Models for Bridging Defects; M. Renovell, et al. 3: Models for Delay Faults; S. M. Reddy. 4: Fault Modeling for Simulation and ATPG; B. Becker, I. Polian. 5: Generalized Fault Modeling for Logic Diagnosis; H.-J. Wunderlich, S. Holst. 6: Models in Memory Testing, From functional testing to defect-based testing; S. Di Carlo, P. Prinetto. 7: Models for Power-Aware Testing; P. Girard, H.-J. Wunderlich. 8: Physical Fault Models and Fault Tolerance; J. Arlat, Y. Crouzet. Index.
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