This book starts with background concerning three-dimensional integration – including their low energy consumption and high speed image processing – and then proceeds to how to construct them and which materials to use in particular situations. The book covers numerous applications, including next generation smart phones, driving assistance systems, capsule endoscopes, homing missiles, and many others. The book concludes with recent progress and developments in three dimensional packaging, as well as future prospects.
Mục lục
Research and Development History of Three Dimensional (3D) Integration Technology.- Recent Research and Development Activities of Three Dimensional (3D) Integration Technology.- TSV Processes.- Wafer and Die Bonding Processes.- Metrology and Inspection.- TSV Characteristics and Reliability: Impact of 3D Integration Processes on Device Reliability.- Trends in 3D Integrated Circuit (3D-IC) Testing Technology.- Dream Chip Project at ASET.
Giới thiệu về tác giả
Kazuo Kondo is Professor at Department of Chemical engineering, Osaka Prefecture University. He took his Ph D in Chemical Engineering at the University of Illinois in 1981. He has worked for Sumitomo Metal Industries, Hokkaido University and Okayama University. He has 200 research publications and 100 patents. His major research is Copper Electrodeposition for TSV. His research extends in various fields not only in electrodeposition, but also in battery and CVD. He is member of Electrochemical Society, IEEE, Society of Chemical engineering Japan, Japanese Institute of Electronics Packaging, Surface Finishing Society of Japan, Materia Japan, Electrochemistry Japan and Japanese Society of Applied Physics.
Morihiro Kada is the invited researcher of The National Institute of Advanced Industrial Science and Technology (AIST) and the part-time researcher of Osaka Prefecture University. Prior to joining to AIST and the university he was the consultant of Association of Super-Advanced Electronics Technologies (ASET). Since April 2007 he has been heading the Japanese national R&D project on 3D-Integration technology as the Project in ASET. Before joining to ASET, he had been the General Manager of the Advanced Packaging Development Department in Sharp Corporation. He has more than forty years experience in semiconductor packaging engineering, with major emphasis on developing chip scale, chip stack package and Three Dimensional-System in Package (3D-Si P) as the pioneer of 3D-Integration technology in the world.
Kenji Takahashi is a Chief Specialist at Memory Packaging Development Department, Memory Division, Semiconductor & Strage Company, Toshiba Corporation. He received a M.E. Degree of from Chemical Engineering at the University of Tokyo in 1984 and Ph.D. from Information Science and Electrical Engineering at Kyushu University in 2010. His major research and development is focused on semiconductor packaging and chip packageinteraction, especially through-silicon via technology. He was the Research Manager of Electronic System Integration Technology Research Department, Association of Super-Advanced Electronics Technologies (ASET). He is a Senior Member of IEEE, a member of Society for Chemical Engineers, Japan, Institute of Electronics, Information and Communication Engineers and Japanese Institute of Electronics Packaging.
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