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Sumit Ahuja & Avinash Lakshminarayana 
Low Power Design with High-Level Power Estimation and Power-Aware Synthesis [PDF ebook] 

Ủng hộ

This book presents novel research techniques, algorithms, methodologies and experimental results for high level power estimation and power aware high-level synthesis. Readers will learn to apply such techniques to enable design flows resulting in shorter time to market and successful low power ASIC/FPGA design.

€96.29
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Mục lục

Introduction.- Related Work.- Background.- Architectural Selection using High Level Synthesis.- Statistical Regression Based Power Models.- Coprocessor Design Space Exploration Using High Level Synthesis.- Regression-based Dynamic Power Estimation for FPGAs.- High Level Simulation Directed RTL Power Estimation.- Applying Verification Collaterals for Accurate Power Estimation.- Power Reduction using High-Level Clock-gating.- Model-Checking to exploit Sequential Clock-gating.- System Level Simulation Guided Approach for Clock-gating.- Conclusions.

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Ngôn ngữ Anh ● định dạng PDF ● Trang 170 ● ISBN 9781461408727 ● Kích thước tập tin 3.8 MB ● Tuổi tác 02-99 năm ● Nhà xuất bản Springer New York ● Thành phố NY ● Quốc gia US ● Được phát hành 2011 ● Có thể tải xuống 24 tháng ● Tiền tệ EUR ● TÔI 2246736 ● Sao chép bảo vệ DRM xã hội

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