Many modern computer systems, including homogeneous and heterogeneous architectures, support shared memory in hardware.
In a shared memory system, each of the processor cores may read and write to a single shared address space. For a shared memory machine, the memory consistency model defines the architecturally visible behavior of its memory system. Consistency definitions provide rules about loads and stores (or memory reads and writes) and how they act upon memory. As part of supporting a memory consistency model, many machines also provide cache coherence protocols that ensure that multiple cached copies of data are kept up-to-date. The goal of this primer is to provide readers with a basic understanding of consistency and coherence. This understanding includes both the issues that must be solved as well as a variety of solutions. We present both high-level concepts as well as specific, concrete examples from real-world systems.
This second edition reflects a decade of advancements since the first edition and includes, among other more modest changes, two new chapters: one on consistency and coherence for non-CPU accelerators (with a focus on GPUs) and one that points to formal work and tools on consistency and coherence.
Table of Content
- Preface to the Second Edition
- Preface to the First Edition
- Introduction to Consistency and Coherence
- Coherence Basics
- Memory Consistency Motivation and Sequential Consistency
- Total Store Order and the x86 Memory Model
- Relaxed Memory Consistency
- Coherence Protocols
- Snooping Coherence Protocols
- Directory Coherence Protocols
- Advanced Topics in Coherence
- Consistency and Coherence for Heterogeneous Systems
- Specifying and Validating Memory Consistency Models and Cache Coherence
- Authors’ Biographies
About the author
Margaret Martonosi is the Hugh Trumbull Adams ’35 Professor of Computer Science at Princeton University, where she has been on the faculty since 1994. She is also Director of the Princeton’s Keller Center for Innovation in Engineering Education, and an A. D. White Visiting Professor-at-Large at Cornell University. From August 2015 through March, 2017, Martonosi was a Jefferson Science Fellow within the U.S. Department of State. Martonosi’s research interests are in computer architecture and mobile computing. Her work has included the widely-used Wattch power modeling tool and the Princeton Zebra Net mobile sensor network project for the design and real-world deployment of zebra tracking collars in Kenya. Her current research focuses on computer architecture and hardware-software interface issues in both classical and quantum computing systems. Martonosi is a Fellow of IEEE and ACM. Her papers have received numerous long-term impact awards including: 2015 ISCA Long-Term Influential Paper Award, 2017 ACM SIGMOBILE Test-of-Time Award, 2017 ACM Sen Sys Test-of-Time Paper award, and the 2018 (Inaugural) HPCA Test-of-Time Paper award. Other notable awards include the 2018 IEEE Computer Society Technical Achievement Award, 2010 Princeton University Graduate Mentoring Award, the 2013 NCWIT Undergraduate Research Mentoring Award, the 2013 Anita Borg Institute Technical Leadership Award, and the 2015 Marie Pistilli Women in EDA Achievement Award. In addition to many archival publications, Martonosi is an inventor on seven granted US patents, and has co-authored two technical reference books on power-aware computer architecture. Martonosi completed her Ph.D. at Stanford University.
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