作者: Frank Hannig

Dirk Koch is a lecturer in the Advanced Processor Technologies Group at the University of Manchester. His main research interest is on run-time reconfigurable systems based on FPGAs, including methods, tools and applications. Current research projects include database acceleration using FPGAs based on stream processing as well as reconfigurable instruction set extensions for CPUs. Dirk was a program co-chair of the FPL2012 conference and he is a program committee member of many FPGA related conferences and workshops. He is author of the book “Partial Reconfiguration on FPGAs, ” he holds two patents, and he has (co-)authored over 50 conference and journal publications.  Frank Hannig leads the Architecture and Compiler Design Group in the CS Department at the Friedrich-Alexander University Erlangen-Nürnberg (FAU), Germany, since 2004. He received a diploma degree in an interdisciplinary course of study in EE and CS from the University of Paderborn, Germany in 2000 and a Ph.D. degree (Dr.-Ing.) in CS from FAU in 2009. His main research interests are the design of massively parallel architectures, ranging from dedicated hardware to multi-core architectures, mapping methodologies for domain-specific computing, and architecture/compiler co-design. Frank has authored or co-authored more than 120 peer-reviewed publications. He serves on the program committees of several international conferences (ARC, ASAP, CODES+ISSS, DATE, DASIP, SAC). Frank is a senior member of the IEEE and an affiliate member of the European Network of Excellence on High Performance and Embedded Architecture and Compilation (Hi PEAC). Daniel Ziener is currently a substitute professor for Cyber-Physical Systems at the Technische Universität Hamburg-Harburg, Germany. From 2010 to 2015, he had led the Reconfigurable Computing Group in the Computer Science Department at Friedrich-Alexander University Erlangen-Nürnberg (FAU), Germany. His main research interests are the usage of partial dynamic reconfiguration of FPGAs, efficient usage of FPGA structures, design of signal processing FPGA cores, reliable and fault tolerant embedded systems, as well as security in FPGA-based systems. Daniel has (co-)authored more than 35 peer-reviewed publications, holds two patents, and serves as a program committee member of several international conferences (DATE, FPL, Reconfig, SPL) as well as a reviewer for several international journals.