This book contains extended and revised versions of the best papers that were presented during the fifteenth edition of the IFIP/IEEE WG10.5 International Conference on Very Large Scale Integration, a global System-on-a-Chip Design & CAD conference. The 15th conference was held at the Georgia Institute of Technology, Atlanta, USA (October 15-17, 2007). Previous conferences have taken place in Edinburgh, Trondheim, Vancouver, Munich, Grenoble, Tokyo, Gramado, Lisbon, Montpellier, Darmstadt, Perth and Nice. The purpose of this conference, sponsored by IFIP TC 10 Working Group 10.5 and by the IEEE Council on Electronic Design Automation (CEDA), is to provide a forum to exchange ideas and show industrial and academic research results in the field of microelectronics design. The current trend toward increasing chip integration and technology process advancements brings about stimulating new challenges both at the physical and system-design levels, as well in the test of these systems. VLSI-So C conferences aim to address these exciting new issues.
表中的内容
Statistical Analysis of Normality of Systematic and Random Variability of Flip-Flop Race Immunity in 130nm and 90nm CMOS Technologies.- Use of Gray Decoding for Implementation of Symmetric Functions.- A Programmable Multi-Dimensional Analog Radial-Basis- Function-Based Classifier.- Compression-based So C Test Infrastructures.- Parametric Structure-Preserving Model Order Reduction.- Re CPU: a Parallel and Pipelined Architecture for Regular Expression Matching.- Qo S in Networks-on-Chip – Beyond Priority and Circuit Switching Techniques.- Accurate Performance Estimation using Circuit Matrix Models in Analog Circuit Synthesis.- Statistical and Numerical Approach for a Computer efficient circuit yield analysis.- SWORD: A SAT like Prover Using Word Level Information.- A new analytical approach of the impact of jitter on continuous time delta sigma converters.- An adaptive genetic algorithm for dynamically reconfigurable modules allocation.- The Hazard-Free Superscalar Pipeline Fast Fourier Transform Architecture and Algorithm.- System and Procesor Design Effort Estimation.- Reconfigurable Acceleration with Binary Compatibility for General Purpose Processors.- First Order, Quasi-Static, SOI Charge Conserving Power Dissipation Model.
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