In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities. This book offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures.
€96.29
Tabla de materias
Network-on-Chip Power Estimation.- Timing.- synchronous/asynchronous communication.- Network-on-Chip link design.- Topology exploration.- Network-on-Chip support for CMP/MPSo Cs.- Network design for 3D stacked logic and memory.- Beyond the wired Network-on-Chip.
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Idioma Inglés ● Formato PDF ● Páginas 287 ● ISBN 9781441969118 ● Tamaño de archivo 15.7 MB ● Editor Cristina Silvano & Marcello Lajolo ● Editorial Springer US ● Ciudad NY ● País US ● Publicado 2010 ● Descargable 24 meses ● Divisa EUR ● ID 2150331 ● Protección de copia DRM social
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