In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities. This book offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures.
€96.29
表中的内容
Network-on-Chip Power Estimation.- Timing.- synchronous/asynchronous communication.- Network-on-Chip link design.- Topology exploration.- Network-on-Chip support for CMP/MPSo Cs.- Network design for 3D stacked logic and memory.- Beyond the wired Network-on-Chip.
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语言 英语 ● 格式 PDF ● 网页 287 ● ISBN 9781441969118 ● 文件大小 15.7 MB ● 编辑 Cristina Silvano & Marcello Lajolo ● 出版者 Springer US ● 市 NY ● 国家 US ● 发布时间 2010 ● 下载 24 个月 ● 货币 EUR ● ID 2150331 ● 复制保护 社会DRM
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